Full Job Description32342BR
INDIA – Delhi
Job Description and Requirements
Job Description:
You will work with Verification IP teams:
To architect effective and efficient test-bench
Strategize verification to promote effective debug.
Build UVM infrastructure including monitors, drivers and scoreboards;
Produce functional coverage and checker coverage;
Monitor dashboards and regressions;
Debug and understand root cause.
We are looking for:
3+ Years’ experience in verification and development of VIP using SV & UVM.
Experience on any protocols.
Sound debugging and communication skills plus positive attitude.
Collaborate with Architects/methodology experts to achieve resolutions on issues or driving discussion from architecture/methodology perspective
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Job Category
Engineering
Country
India
Job Subcategory
R&D Engineering
Hire Type
Employee