Silicon Labs Hiring for Associate Staff – SoC/Chip Design Engineer at Hyderabad, Telangana Full Time

We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives. silabs.com

Job Description:
The position involves development of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, Security accelerators, interconnects, memory architecture and data & instruction caches, multiple clocks and resets, high-speed interfaces, peripherals. The chosen candidate would need to contribute to the development of architecture, microarchitecture and design of SoCs which include ARM Cortex M33 processor and proprietary processor designs, AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I2C, PWM and high-speed interfaces for off-chip memories. The chosen candidate would be responsible for the entire design flow and sign-off, including design, synthesis, and STA, and be able to deliver reusable and robust IP.

Experience Level:
8-10 years

Education Requirements:
B.Tech/M.Tech in ECE, EEE

Minimum Qualifications:
Capable of leading complex IP, SOC development projects execution.

Top-down planning and execution of SOC projects.

Should have experience in full-chip development cycle

Able to build strong technical team.

Hands-on experience in architecture, micro-architecture, digital design processes

Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI

Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.

Knowledge of processors like RISC-V and ARM processors

Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure

Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)

Knowledge of hardware accelerators

Knowledge of Verilog and System Verilog

Analytical debugging skills

Knowledge of SoC, Memory and Cache Architectures

Preferred Qualifications:
Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee

Knowledge of DFT including Scan, MBIST

Mentoring skills

Exceptional problem-solving skills

Good written and oral communication skills

Knowledge of scripting languages like Perl, Python, Tcl, shell

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Benefits & Perks

Equity Rewards (RSUs)

Insurance plans

PF and NPS

WFH Options